1. 1. Field of the Invention
The present invention pertains to a voltage switch-over circuit in MOS technology. It pertains more particularly to a voltage switch-over circuit in MOS technology which, depending on a switch-over signal, delivers either a first voltage Vpp or a second voltage Vcc at its output, the voltage Vpp being greater than the voltage Vcc.
2. Description of the Prior Art
This type of switch-over circuit is used especially to program or read EPROM or EEPROM type memories, the memory cell of which is formed by a floating-gate MOS transistor. Thus, as shown in FIG. 1 which pertains to an EPROM memory, the memory cell 1 of which consists of a SAMOS (stacked gate avalanche injection MOS) type floating-gate transistor, each floating-gate transistor 1 has two main electrodes, 2 and 3 respectively, and a control gate 5 stacked on the floating gate 4. In the case of a memory, the floating-gate transistors 1 which constitute the memory cells are connected in matrix form. Thus, a first main electrode 2 or source, in the technology used, is connected to the ground while the other electrode 3 or drain is connected by a bit line (not shown) and a MOS transistor forming a switch 8 to a column address decoder 9. The control gate 5 is connected by another connection, called a word line (not shown), to a row address decoder 7.
More specifically, the column address decoder 9 is connected to the gate of the transistor 8, which has its source connected to the electrode 3 of the floating-gate MOS transistor 1 while its other electrode or drain is connected by a load line, consisting of the MOS transistors 11 and 12, to the programming voltage Vpp. The load line consists of a depleted MOS transistor 12 which has its drain connected to Vpp and its source connected to the drain of an enhanced MOS transistor 11, the two gates of the transistors 11 and 12 being connected to each other and to the write control circuit 13. Furthermore, the node N between the MOS transistor 11 and the drain of the MOS transistor 8 is connected to a read amplifier represented by the block 10.
Similarly, the row address decoder 7 is connected to the gate of the switch MOS transistor 6 which has one of its main electrodes connected to the control gate 5 of the floating-gate MOS transistor 1 while its other main electrode is connected to the output of a voltage switch-over circuit.
As shown in FIG. 1 the voltage switch-over circuit, which is used to switch over the voltage at the output S either to the voltage Vpp or to the voltage Vcc, consists essentially of two depleted MOS transistors 14 and 15, mounted between the supply voltage Vcc and the programming voltage Vpp. More specifically, the drain of the depleted transistor 14 is connected to Vpp. Its source is connected to the source of the depleted transistor 15 wich has its drain connected to the voltage Vcc. The output of the switch-over circuit is made at the midpoint S between the two depleted MOS transistors 14 and 15. Furthermore, the gates of the two depleted transistors 14 and 15 are respectively connected to the outputs Q and Q of an RS flip-flop 16. This flip-flop 16 is made, for example, by means of two cross-coupled NOR gates 27 and 28, i.e. one of the inputs of the NOR gate 27 is connected to the output of the NOR gate 28, and one of the inputs of the NOR gate 28 is connected to the output of the NOR gate 27. Furthermore, the NOR gate 27 is supplied by the supply voltage Vcc while the NOR gate 28 is supplied by the programming voltage Vpp. The other inputs of the NOR gates 27 and 28 are respectively connected to the programming control signal PGM and the inverted programming control signal PGM obtained at the output of the inverter 19.
To read a memory cell of the type shown in FIG. 1, a voltage equal to the supply voltage Vcc should be applied to the control gate 5. This voltage comes from the switch-over circuit. Consequently, the signal at the output S is at the voltage Vcc. Now the supply voltage Vcc is generally chosen as being equal to 5 volts while the programming voltage Vpp is most usually equal to 21 volts in the technology used, but must bear voltages equal to at least 23 volts. The result of this is that the voltage strength of the MOS transistor 14 should be equal to at least Vpp-Vcc, i.e. it should be greater than 18 volts. Now, with currently used technologies, it is difficult to make MOS transistors having this degree of voltage strength. Consequently, a problem of breakdown is frequently observed, and this problem makes the switch-over circuit unusable.
An object of the present invention, therefore, is to remove this disadvantage by proposing a new voltage switch-over circuit in MOS technology.
3. Summary of the Invention
Thus, an object of the present invention is a voltage switch-over circuit in MOC technology which, depending on a switch-over signal, delivers either a first voltage Vpp or a second voltage Vcc at its output, the voltage Vpp being greater than the voltage Vcc, the said circuit comprising a first MOS transistor having one of its electrodes connected to the voltage Vcc and a set of two series-connected MOS transistors which has one of its electrodes connected to the voltage Vpp and has its two gates connected together, so as to create a floating node at the common point between the two MOS transistors, the other electrode of the first MOS transistor and the other similar electrode of the set of two MOS transistors being connected together, and the gates of the first MOS transistoor and those of the set of two MOS transistors respectively receiving the switch-over signal and the reserved switch-over signal.